1. Field of the Invention
The present general inventive concept disclosed herein relates to a semiconductor, and more particularly, to a semiconductor package with an improved reliability, and an electronic device having the same.
2. Description of the Related Art
Generally, a semiconductor package has a structure that a semiconductor chip is protected from an external environment by being molded with an epoxy molding compound (EMC). FIG. 1 is a top plan view illustrating a conventional semiconductor package. Referring to FIG. 1, a semiconductor chip 11 includes a plurality of die pads 13, and the die pads 13 are electrically connected to outer terminals 14 by interconnections 15. The semiconductor chip 11 is molded with a molding layer 12 such as an epoxy molding compound (EMC). A semiconductor package 10 is electrically connected to an external device through the outer terminal 14.
An interface 16 is formed between the semiconductor chip 11 and the molding layer 12. Since the semiconductor chip 11 and the molding layer 12 have different materials, a physical characteristic such as a mechanical characteristic and a thermal characteristic may be different. A mechanical stress or a thermal stress which is applied to a semiconductor package 10 may be concentrated on the interface 16. If a mechanical stress or a thermal stress is concentrated on the interface 16, a crack may occur at the interface 16, or a lamination phenomenon in which the semiconductor chip 11 and the molding layer 12 are separated from each other may occur. A crack or a lamination phenomenon may cause a crack of the interconnection 15 or a disconnection of the interconnection 15. Thus, a reduction in reliability of the semiconductor package 10, such as an electrical malfunction, may occur.